Erwin Ofner, Chi Zhang, Haifeng Zhou: "Integration of Low-Power Decimation Filters", 3. Forschungsforum der österreichischen Fachhochschulen, April 2009, Villach, pp147-151, ISBN 978-3-853912850.

 

The need for extended operation and standby times in modern battery powered electronic equipment requires advanced low power design methods. This paper describes research activities in two projects, both targeted at low power integration of digital functions frequently used in components for popular consumer applications. While work in a project which has already been completed, delivered low power digital modules for 3rd generation mobile phones, quite similar low power components have been developed for portable digital audio circuits like MP3 players – often integrated into mobile phones as well. Two design examples are given: the design of a multi-mode decimation filter for the Analog to Digital Converter (ADC) of a GSM/UMTS mobile terminal and the design of a test vehicle for an ultra low power decimation filter for the ADC in portable digital audio equipment. In both cases new low power filter architectures and circuits were designed, fabricated on testchips and evaluated to reach attractive results.

 

Wolfgang Aichholzer, Johannes Sturm: "A 65nm CMOS RF Power Detector with Integrated Offset Storage", in Proceedings of Austrochip 2009, Oct. 2009, Graz, pp5-8, ISBN 978-3-9501635-1-3.

 

In this work we present a fully differential and symmetric power detector (PD) used for mobile applications. The information of the signal power is used in an automatic gain control circuit (AGC) to maintain the low-noise RF amplifier’s (LNA) gain to avoid saturation problems. The proposed PD structure uses a fully differential rectifier structure based on "self-mixing" technique. The circuit uses an offset storage method to improve the offset voltage and is implemented in 65nm CMOS technology.

Oleksandr Melnychenko, Sergii Zaiets, Manfred Ley: "Low-Power High-Speed Decimation Filter in 65 nm CMOS", in Proceedings of Austrochip 2009, Oct. 2009, Graz, pp75-79, ISBN 978-3-9501635-1-3.

 

The design and implementation of a high-speed low power decimation filter using a deep-sub-micron digital standard cell library is presented. The choice of a polyphase non-recursive decimation filter is explained and some flexibility of the polyphase decimation filter implementation is demonstrated. The description starts from

system level and goes via synthesis and layout to the backannotated circuit simulation. Some problems of synthesis

and routing influencing the design are discussed. Finally results after layout and their analysis are presented, which demonstrate the correct work of the designed decimation filter at the specified clock speed of 2.56 GHz with a power consumption of 1.2 mW.